Simulation of an integrated circuit (IC) design such as System-on-Chip (SOC) or an application-specific integrated circuit (ASIC) requires a verification environment for a plurality of register-transfer level (RTL) modules in the design. At an abstract level, the verification environment can be viewed as a composition of a plurality of tests, which run during the simulation in addition to monitoring and detection mechanisms. The RTL modules and the verification environment are living entities during the life of the IC design project and evolve with the project. Each of the plurality of RTL modules may have multiple instances and is holistic in the sense that the sum of its instances is greater than its parts, implying mutual dependencies of the RTL instances to achieve the goals of the overall IC design implementation.
Whenever a portion of the IC design changes at the RTL level, the IC designer needs to ensure that first, the new functionality is working and secondly, it has not broken any other pieces in the design. The first part can be tested using resolution tests and second part is tested through regressions. Both sets of tests are a subset of tests created by the experts of the IC design. Regressions typically incur the largest costs in the IC design projects in terms of time, simulation, compute and human resources. As such, it is important to determine that, when RTL modules have been changed, which subset of available tests should be run for regression in order to ascertain the two objectives above while taking minimal resources in terms of time, computes, licenses etc.
Although a static analysis of the RTL modules can yield the dependencies among the RTL modules, regression tests for verification are dynamic with constraints and random seeds. Therefore, a regression test generation approach that can analyze the dynamics of the IC design in order to provide better insight is desired.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent upon a reading of the specification and a study of the drawings.